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Intel Details 288-Core Clearwater Forest CPU with 17-Chiplet Design at Hot Chips 2025

Michele Adams

At this year’s Hot Chips conference, Intel has pulled back the curtain on Clearwater Forest, its next-generation Xeon processor featuring efficiency-optimized E-cores. While stacked 3D cache was long considered AMD’s secret sauce for major performance boosts, Intel is now showcasing its own unique and powerful approach. Following its predecessor, Sierra Forest, the new Xeon 6900E is set to pack up to 288 cores into a single socket, promising a significant leap in performance without relying on hyperthreading.

This advancement is driven by a combination of the cutting-edge Intel 18A process and a sophisticated new level of advanced packaging. The Clearwater Forest processors are constructed from three distinct layers of silicon stacked on top of each other, creating a complex and powerful multi-chiplet design.

A New Era of 3D Packaging

The top layer of the processor consists of the CPU chiplets, each containing 24 processor cores and 24 MB of L2 cache, all manufactured on the Intel 18A process. A notable detail is the relatively small size of these chiplets compared to previous Xeon generations. This strategic decision allows Intel to achieve a higher yield of functional dies from its newest manufacturing process. Four of these CPU chiplets can be mounted onto a base chiplet using Intel’s Foveros Direct technology, which enables direct copper-to-copper bonding for high-speed communication.

Uniting Three Generations of Manufacturing

Beneath the CPU chiplets lies the base chiplet, which is produced using the Intel 3 process—the same technology currently used for the compute dies in Sapphire Rapids. This layer houses the L3 cache, referred to as the Last Level Cache (LLC), along with the system fabric and memory controllers. The LLC sees a substantial increase compared to its predecessor, with each base chiplet containing 192 MB of cache. The bottom layer of this 3D package features two I/O chiplets produced on the even more mature Intel 7 process, which manage high-speed I/O, fabric, and specialized accelerator units.

All told, a single Clearwater Forest processor is a complex assembly of 17 individual chiplets, leveraging three different manufacturing processes to optimize performance and production efficiency.

Core Improvements and a Focus on Throughput

The CPU cores themselves, codenamed “Darkmont,” are arranged in modules of four, which share a unified 4 MB L2 cache. Intel projects that these new cores will deliver a 17% increase in Instructions Per Cycle (IPC), based on SPECintrate_2017 benchmarks, while the L2 cache throughput has been doubled to an impressive 400 GB/s. A full system with 12 of these 24-core chiplets brings the total to 288 cores.

While Intel isn’t releasing raw performance benchmarks just yet—as the focus for E-core Xeons is on throughput and efficiency—the data transfer speeds are staggering. The company highlighted several key metrics:

  • Last Level Cache (LLC): 5 TB/s

  • DDR5 Memory Interface: 1.3 TB/s (from a 12-channel interface supporting 8,000 MT/s)

  • PCIe 5.0 and CXL: 1 TB/s combined

  • Ultra Path Interconnect (UPI): 576 GB/s

In a dual-socket (2P) configuration, a system can feature a massive 576 cores and 1,152 MB of LLC. Part of Intel’s two-pronged server strategy, Clearwater Forest is slated to launch by 2026, following the current Granite Rapids (P-core) and Sierra Forest (E-core) processors.